1. Technical Field
The invention relates generally to semiconductor devices, and more specifically, to wafer-level testing and burn-in for semiconductor devices.
2. Background Art
Prior to shipping, semiconductor devices are generally subjected to a series of test procedures in order to confirm functionality and yield, and to assure quality and reliability. This testing procedure conventionally includes probe testing and burn-in testing, which are generally done after a wafer is diced into individual chips, and many times, after the chips are packaged.
Considerable interest exists in methods for performing wafer-level burn-in of semiconductor devices to determine known good die per wafer before wafers are separated into individual chips. Examples of wafer-level testing are found in the following U.S. Patents: U.S. Pat. No. 5,661,042, "Process for Electrically Connecting Electrical Devices Using a Conductive Anisotropic Material," issued to Fang et al.; and U.S. Pat. No. 5,663,654, "Universal Wafer Carrier for Wafer Level Die Burn-In," issued to Wood et al. In the aforementioned patents, electrical contact is made between a semiconductor wafer and the test or probe substrate through conductive material to allow for wafer-level testing.
Unfortunately, the conductive material described is deposited over the entire wafer, not allowing for selective testing of the wafer. Furthermore, the conductive material is generally temporary, not providing for a possible permanent connection between the substrate and the wafer. Also, after a defect is found, the wafer then may be diced up, and the chip(s) identified on the wafer as defective may then be thrown out, but there is no convenient way to repair and rework the defective wafer at wafer-level.